forked from mirrors/qmk_userspace
Added wireless support; Added Lemokey L3; Added Keychron V1 Max
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lokher
parent
9539f135d8
commit
4ae5990fcc
31585 changed files with 99327 additions and 1763186 deletions
330
keyboards/keychron/bluetooth/lpm_stm32l432.c
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330
keyboards/keychron/bluetooth/lpm_stm32l432.c
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/* Copyright 2022 @ lokher (https://www.keychron.com)
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/******************************************************************************
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*
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* Filename: lpm_stm32l432.c
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*
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* Description: Contains low power mode implementation
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*
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******************************************************************************/
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#include "quantum.h"
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#include <usb_main.h>
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#include "bluetooth.h"
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#include "indicator.h"
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#include "lpm.h"
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#include "transport.h"
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#include "battery.h"
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#include "report_buffer.h"
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#include "stm32_bd.inc"
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#include "debounce.h"
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extern pin_t row_pins[MATRIX_ROWS];
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extern void select_all_cols(void);
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extern bluetooth_transport_t bluetooth_transport;
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static pm_t power_mode = PM_RUN;
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static inline void stm32_clock_fast_init(void);
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bool lpm_set(pm_t mode) {
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switch (mode) {
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#ifdef LOW_POWER_RUN_MODE_ENABLE
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case PM_RUN:
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if (power_mode != PM_LOW_POWER_RUN)) return;
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/* Set main regulator */
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PWR->CR1 &= ~PWR_CR1_LPR;
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while (PWR->SR2 & PWR_SR2_REGLPF)
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;
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// TODO: restore sysclk
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return true;
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// break;
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case PM_LOW_POWER_RUN:
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if (power_mode != PM_RUN) return;
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// FLASH->ACR |= FLASH_ACR_RUN_PD; // Optional
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// TODO: Decrease sysclk below 2 MHz
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PWR->CR1 |= PWR_CR1_LPR;
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return true;
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// break;
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#endif
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case PM_SLEEP:
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/* Wake source: Any interrupt or event */
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if (power_mode != PM_RUN) return false;
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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break;
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#ifdef LOW_POWER_RUN_MODE_ENABLE
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case PM_LOW_POWER_SLEEP:
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/* Wake source: Any interrupt or event */
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if (power_mode != PM_LOW_POWER_RUN) return; /* Can only transit from PM_LOW_POWER_RUN */
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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__WFI();
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exit_low_power_mode();
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break;
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#endif
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case PM_STOP0:
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/* Wake source: Reset pin, all I/Os, BOR, PVD, PVM, RTC, LCD, IWDG,
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COMPx, USARTx, LPUART1, I2Cx, LPTIMx, USB, SWPMI */
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if (power_mode != PM_RUN) return false;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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PWR->CR1 |= PWR_CR1_LPMS_STOP0;
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break;
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case PM_STOP1:
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/* Wake source: Reset pin, all I/Os, BOR, PVD, PVM, RTC, LCD, IWDG,
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COMPx, USARTx, LPUART1, I2Cx, LPTIMx, USB, SWPMI */
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if (power_mode != PM_RUN && power_mode != PM_LOW_POWER_RUN) return false;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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PWR->CR1 |= PWR_CR1_LPMS_STOP1;
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break;
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case PM_STOP2:
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/* Wake source: Reset pin, all I/Os, BOR, PVD, PVM, RTC, LCD, IWDG,
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COMPx (x=1, 2), I2C3, LPUART1, LPTIM1, LPTIM2 */
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if (power_mode != PM_RUN) return false;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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PWR->CR1 |= PWR_CR1_LPMS_STOP2;
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break;
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case PM_STANDBY_WITH_RAM:
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/* Wake source: Reset, 5 I/O(PA0, PC13, PE6, PA2, PC5), BOR, RTC, IWDG */
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if (power_mode != PM_RUN && power_mode != PM_LOW_POWER_RUN) return false;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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PWR->CR1 |= PWR_CR1_LPMS_STANDBY;
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PWR->CR3 |= PWR_CR3_RRS;
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break;
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case PM_STANDBY:
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/* Wake source: Reset, 2 I/O(PA0, PA2) in STM32L432Kx,, BOR, RTC, IWDG */
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if (power_mode != PM_RUN && power_mode != PM_LOW_POWER_RUN) return false;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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PWR->CR1 |= PWR_CR1_LPMS_STANDBY;
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PWR->CR3 &= ~PWR_CR3_RRS;
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break;
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case PM_SHUTDOWN:
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/* Wake source: Reset, 2 I/O(PA0, PA2) in STM32L432Kx, RTC */
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if (power_mode != PM_RUN && power_mode != PM_LOW_POWER_RUN) return false;
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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PWR->CR1 |= PWR_CR1_LPMS_SHUTDOWN;
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break;
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default:
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return false;
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}
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return true;
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}
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static inline void enter_low_power_mode_prepare(void) {
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#if defined(KEEP_USB_CONNECTION_IN_BLUETOOTH_MODE)
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/* Usb unit is actived and running, stop and disconnect first */
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usbStop(&USBD1);
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usbDisconnectBus(&USBD1);
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/* Isolate USB to save power.*/
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PWR->CR2 &= ~PWR_CR2_USV; /*PWR_CR2_USV is available on STM32L4x2xx and STM32L4x3xx devices only. */
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#endif
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palEnableLineEvent(BLUETOOTH_INT_INPUT_PIN, PAL_EVENT_MODE_FALLING_EDGE);
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palEnableLineEvent(USB_POWER_SENSE_PIN, PAL_EVENT_MODE_BOTH_EDGES);
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/* Enable key matrix wake up */
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pin_t row_pins[MATRIX_ROWS] = MATRIX_ROW_PINS;
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for (uint8_t x = 0; x < MATRIX_ROWS; x++) {
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if (row_pins[x] != NO_PIN) {
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palEnableLineEvent(row_pins[x], PAL_EVENT_MODE_BOTH_EDGES);
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}
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}
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select_all_cols();
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#if defined(DIP_SWITCH_PINS)
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# define NUMBER_OF_DIP_SWITCHES (sizeof(dip_switch_pad) / sizeof(pin_t))
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static pin_t dip_switch_pad[] = DIP_SWITCH_PINS;
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for (uint8_t i = 0; i < NUMBER_OF_DIP_SWITCHES; i++) {
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setPinInputLow(dip_switch_pad[i]);
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}
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#endif
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}
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static inline void lpm_wakeup(void) {
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chSysLock();
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stm32_clock_fast_init();
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chSysUnlock();
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if (bluetooth_transport.init) bluetooth_transport.init(true);
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chSysLock();
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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PWR->SCR |= PWR_SCR_CWUF;
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PWR->SCR |= PWR_SCR_CSBF;
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/* TIMx is disable during stop/standby/sleep mode, init after wakeup */
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stInit();
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timer_init();
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chSysUnlock();
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battery_init();
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/* Disable all wake up pins */
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for (uint8_t x = 0; x < MATRIX_ROWS; x++) {
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if (row_pins[x] != NO_PIN) {
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palDisableLineEvent(row_pins[x]);
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}
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}
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palDisableLineEvent(BLUETOOTH_INT_INPUT_PIN);
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#ifdef USB_POWER_SENSE_PIN
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palDisableLineEvent(USB_POWER_SENSE_PIN);
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# if defined(KEEP_USB_CONNECTION_IN_BLUETOOTH_MODE)
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if (usb_power_connected()) {
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hsi48_init();
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/* Remove USB isolation.*/
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// PWR->CR2 |= PWR_CR2_USV; /* PWR_CR2_USV is available on STM32L4x2xx and STM32L4x3xx devices only. */
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usb_power_connect();
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usb_start(&USBD1);
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}
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# endif
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#endif
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#if defined(DIP_SWITCH_PINS)
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dip_switch_init();
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dip_switch_read(true);
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#endif
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}
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/*
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* NOTE:
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* 1. Shall not use PM_LOW_POWER_RUN, PM_LOW_POWER_SLEEP, due to PM_LOW_POWER_RUN
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* need to decrease system clock below 2 MHz. Dynamic clock is not yet supported
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* for STM32L432xx in latest ChibiOS 21.6.0 so far.
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* 2. Care must be taken to use PM_STANDBY_WITH_RAM, PM_STANDBY, PM_SHUTDOWN due to
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* limited wake source, thus can't be waken via keyscan. PM_SHUTDOWN need LSE.
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* 3. Reference from AN4621: STM32L4 and STM32L4+ ultra-low-power features overview
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* for detail wake source
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*/
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void enter_power_mode(pm_t mode) {
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#if defined(KEEP_USB_CONNECTION_IN_BLUETOOTH_MODE)
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/* Don't enter low power mode if attached to the host */
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if (mode > PM_SLEEP && usb_power_connected()) return;
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#endif
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if (!lpm_set(mode)) return;
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enter_low_power_mode_prepare();
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// __DSB();
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__WFI();
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// __ISB();
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lpm_wakeup();
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lpm_timer_reset();
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report_buffer_init();
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/* Call debounce_free() to avoid memory leak as debounce_init() invoked in matrix_init() allocates
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* new memory when using per row/key debounce
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*/
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debounce_free();
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matrix_init();
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power_mode = PM_RUN;
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}
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void usb_power_connect(void) {
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PWR->CR2 |= PWR_CR2_USV;
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}
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void usb_power_disconnect(void) {
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PWR->CR2 &= ~PWR_CR2_USV;
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}
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/*
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* This is a simplified version of stm32_clock_init() by removing unnecessary clock initlization
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* code snippet. The original stm32_clock_init() take about 2ms, but ckbt51 sends data via uart
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* about 200us after wakeup pin is assert, it means that we must get everything ready before data
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* coming when wakeup pin interrupt of MCU is triggerred.
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* Here we reduce clock init time to less than 100us.
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*/
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void stm32_clock_fast_init(void) {
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#if !STM32_NO_INIT
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/* Clocks setup.*/
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msi_init(); // 6.x us
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hsi16_init(); // 4.x us
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/* PLLs activation, if required.*/
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pll_init();
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pllsai1_init();
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pllsai2_init();
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/* clang-format off */
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
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STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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/* CCIPR register initialization, note, must take care of the _OFF
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pseudo settings.*/
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{
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uint32_t ccipr = STM32_DFSDMSEL | STM32_SWPMI1SEL | STM32_ADCSEL |
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STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
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STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
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STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
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STM32_USART2SEL | STM32_USART1SEL | STM32_LPUART1SEL;
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/* clang-format on */
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# if STM32_SAI2SEL != STM32_SAI2SEL_OFF
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ccipr |= STM32_SAI2SEL;
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# endif
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# if STM32_SAI1SEL != STM32_SAI1SEL_OFF
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ccipr |= STM32_SAI1SEL;
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# endif
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RCC->CCIPR = ccipr;
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}
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/* Set flash WS's for SYSCLK source */
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if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
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FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
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while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
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}
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}
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/* Switching to the configured SYSCLK source if it is different from MSI.*/
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# if (STM32_SW != STM32_SW_MSI)
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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/* Wait until SYSCLK is stable.*/
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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# endif
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/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
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if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
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FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | STM32_FLASHBITS;
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while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
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}
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}
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#endif /* STM32_NO_INIT */
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}
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