forked from mirrors/qmk_userspace
		
	Add support for STM32F407x MCUs. (#13718)
* Add support for STM32F407x MCUs. * Removing STMF407 MCU variation * Update quantum/mcu_selection.mk Remove options for dfu flashing Co-authored-by: Ryan <fauxpark@gmail.com> * DISABLE STM32_USB_USE_OTG1 * Update platforms/chibios/GENERIC_STM32_F407XE/configs/mcuconf.h Co-authored-by: Drashna Jaelre <drashna@live.com> * Update platforms/chibios/GENERIC_STM32_F407XE/configs/mcuconf.h Co-authored-by: thomas.pollak <thomas.pollak@dynatrace.com> Co-authored-by: Ryan <fauxpark@gmail.com> Co-authored-by: Drashna Jaelre <drashna@live.com> Co-authored-by: Nick Brassel <nick@tzarc.org>
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					 9 changed files with 447 additions and 2 deletions
				
			
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			@ -13,7 +13,7 @@
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        },
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        "processor": {
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            "type": "string",
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            "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L412", "STM32L422", "STM32L433", "STM32L443", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"]
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            "enum": ["cortex-m0", "cortex-m0plus", "cortex-m3", "cortex-m4", "MKL26Z64", "MK20DX128", "MK20DX256", "MK66F18", "STM32F042", "STM32F072", "STM32F103", "STM32F303", "STM32F401", "STM32F407", "STM32F411", "STM32F446", "STM32G431", "STM32G474", "STM32L412", "STM32L422", "STM32L433", "STM32L443", "atmega16u2", "atmega32u2", "atmega16u4", "atmega32u4", "at90usb162", "at90usb646", "at90usb647", "at90usb1286", "at90usb1287", "atmega32a", "atmega328p", "atmega328", "attiny85", "unknown"]
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        },
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        "board": {
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            "type": "string",
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			@ -27,6 +27,7 @@ You can also use any ARM chip with USB that [ChibiOS](https://www.chibios.org) s
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 * [STM32F103](https://www.st.com/en/microcontrollers-microprocessors/stm32f103.html)
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 * [STM32F303](https://www.st.com/en/microcontrollers-microprocessors/stm32f303.html)
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 * [STM32F401](https://www.st.com/en/microcontrollers-microprocessors/stm32f401.html)
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 * [STM32F407](https://www.st.com/en/microcontrollers-microprocessors/stm32f407-417.html)
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 * [STM32F411](https://www.st.com/en/microcontrollers-microprocessors/stm32f411.html)
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 * [STM32F446](https://www.st.com/en/microcontrollers-microprocessors/stm32f446.html)
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 * [STM32G431](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x1.html)
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			@ -32,6 +32,7 @@ QMK は十分な容量のフラッシュメモリを備えた USB 対応 AVR ま
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* [STM32F103](https://www.st.com/en/microcontrollers-microprocessors/stm32f103.html)
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* [STM32F303](https://www.st.com/en/microcontrollers-microprocessors/stm32f303.html)
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* [STM32F401](https://www.st.com/en/microcontrollers-microprocessors/stm32f401.html)
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* [STM32F407](https://www.st.com/en/microcontrollers-microprocessors/stm32f407-417.html)
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* [STM32F411](https://www.st.com/en/microcontrollers-microprocessors/stm32f411.html)
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* [STM32F446](https://www.st.com/en/microcontrollers-microprocessors/stm32f446.html)
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* [STM32G431](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x1.html)
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			@ -13,7 +13,7 @@ QMK_FIRMWARE_UPSTREAM = 'qmk/qmk_firmware'
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MAX_KEYBOARD_SUBFOLDERS = 5
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# Supported processor types
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CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66F18', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L412', 'STM32L422', 'STM32L433', 'STM32L443'
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CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK66F18', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L412', 'STM32L422', 'STM32L433', 'STM32L443'
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LUFA_PROCESSORS = 'at90usb162', 'atmega16u2', 'atmega32u2', 'atmega16u4', 'atmega32u4', 'at90usb646', 'at90usb647', 'at90usb1286', 'at90usb1287', None
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VUSB_PROCESSORS = 'atmega32a', 'atmega328p', 'atmega328', 'attiny85'
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										9
									
								
								platforms/chibios/GENERIC_STM32_F407XE/board/board.mk
									
										
									
									
									
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								platforms/chibios/GENERIC_STM32_F407XE/board/board.mk
									
										
									
									
									
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			@ -0,0 +1,9 @@
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# List of all the board related files.
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
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# Required include directories
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BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC  += $(BOARDINC)
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								platforms/chibios/GENERIC_STM32_F407XE/configs/board.h
									
										
									
									
									
										Normal file
									
								
							
							
						
						
									
										24
									
								
								platforms/chibios/GENERIC_STM32_F407XE/configs/board.h
									
										
									
									
									
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			@ -0,0 +1,24 @@
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/* Copyright 2020 Nick Brassel (tzarc)
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 *
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 *  This program is free software: you can redistribute it and/or modify
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 *  it under the terms of the GNU General Public License as published by
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 *  the Free Software Foundation, either version 3 of the License, or
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 *  (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *  GNU General Public License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
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 */
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#pragma once
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#define STM32_HSECLK 8000000
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// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix:
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#define BOARD_OTG_NOVBUSSENS
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#include_next "board.h"
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#undef STM32_HSE_BYPASS
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								platforms/chibios/GENERIC_STM32_F407XE/configs/config.h
									
										
									
									
									
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								platforms/chibios/GENERIC_STM32_F407XE/configs/config.h
									
										
									
									
									
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			@ -0,0 +1,23 @@
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/* Copyright 2021 Andrei Purdea
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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		||||
 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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/* Address for jumping to bootloader on STM32 chips. */
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/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
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 */
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#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
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#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
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#    define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
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#endif
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										355
									
								
								platforms/chibios/GENERIC_STM32_F407XE/configs/mcuconf.h
									
										
									
									
									
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								platforms/chibios/GENERIC_STM32_F407XE/configs/mcuconf.h
									
										
									
									
									
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			@ -0,0 +1,355 @@
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/*
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    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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    Licensed under the Apache License, Version 2.0 (the "License");
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    you may not use this file except in compliance with the License.
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    You may obtain a copy of the License at
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        http://www.apache.org/licenses/LICENSE-2.0
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    Unless required by applicable law or agreed to in writing, software
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    distributed under the License is distributed on an "AS IS" BASIS,
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    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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    See the License for the specific language governing permissions and
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    limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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 * STM32F4xx drivers configuration.
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 * The following settings override the default settings present in
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 * the various device driver implementation headers.
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 * Note that the settings for each driver only have effect if the whole
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 * driver is enabled in halconf.h.
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 *
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 * IRQ priorities:
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 * 15...0       Lowest...Highest.
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 *
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 * DMA priorities:
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 * 0...3        Lowest...Highest.
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 */
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#define STM32F4xx_MCUCONF
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#define STM32F405_MCUCONF
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#define STM32F415_MCUCONF
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#define STM32F407_MCUCONF
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#define STM32F417_MCUCONF
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/*
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 * HAL driver system settings.
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 */
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#define STM32_NO_INIT                       FALSE
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#define STM32_PVD_ENABLE                    FALSE
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#define STM32_PLS                           STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE                 FALSE
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#define STM32_HSI_ENABLED                   TRUE
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#define STM32_LSI_ENABLED                   TRUE
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#define STM32_HSE_ENABLED                   TRUE
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#define STM32_LSE_ENABLED                   FALSE
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#define STM32_CLOCK48_REQUIRED              TRUE
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#define STM32_SW                            STM32_SW_PLL
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#define STM32_PLLSRC                        STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE                    8
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#define STM32_PLLN_VALUE                    336
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#define STM32_PLLP_VALUE                    2
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#define STM32_PLLQ_VALUE                    7
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#define STM32_HPRE                          STM32_HPRE_DIV1
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#define STM32_PPRE1                         STM32_PPRE1_DIV4
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#define STM32_PPRE2                         STM32_PPRE2_DIV2
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#define STM32_RTCSEL                        STM32_RTCSEL_LSI
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#define STM32_RTCPRE_VALUE                  8
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#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE                 192
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#define STM32_PLLI2SR_VALUE                 5
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/*
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 * IRQ system settings.
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 */
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#define STM32_IRQ_EXTI0_PRIORITY            6
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#define STM32_IRQ_EXTI1_PRIORITY            6
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#define STM32_IRQ_EXTI2_PRIORITY            6
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#define STM32_IRQ_EXTI3_PRIORITY            6
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#define STM32_IRQ_EXTI4_PRIORITY            6
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#define STM32_IRQ_EXTI5_9_PRIORITY          6
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#define STM32_IRQ_EXTI10_15_PRIORITY        6
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#define STM32_IRQ_EXTI16_PRIORITY           6
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#define STM32_IRQ_EXTI17_PRIORITY           15
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#define STM32_IRQ_EXTI18_PRIORITY           6
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#define STM32_IRQ_EXTI19_PRIORITY           6
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#define STM32_IRQ_EXTI20_PRIORITY           6
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#define STM32_IRQ_EXTI21_PRIORITY           15
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#define STM32_IRQ_EXTI22_PRIORITY           15
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/*
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 * ADC driver system settings.
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 */
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#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
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#define STM32_ADC_USE_ADC1                  FALSE
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#define STM32_ADC_USE_ADC2                  FALSE
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#define STM32_ADC_USE_ADC3                  FALSE
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#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
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#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
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#define STM32_ADC_ADC1_DMA_PRIORITY         2
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#define STM32_ADC_ADC2_DMA_PRIORITY         2
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#define STM32_ADC_ADC3_DMA_PRIORITY         2
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#define STM32_ADC_IRQ_PRIORITY              6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6
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/*
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 * CAN driver system settings.
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 */
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#define STM32_CAN_USE_CAN1                  FALSE
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#define STM32_CAN_USE_CAN2                  FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY         11
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#define STM32_CAN_CAN2_IRQ_PRIORITY         11
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/*
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 * DAC driver system settings.
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 */
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#define STM32_DAC_DUAL_MODE                 FALSE
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#define STM32_DAC_USE_DAC1_CH1              FALSE
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#define STM32_DAC_USE_DAC1_CH2              FALSE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
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#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 5)
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#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 6)
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/*
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 * GPT driver system settings.
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 */
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#define STM32_GPT_USE_TIM1                  FALSE
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#define STM32_GPT_USE_TIM2                  FALSE
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#define STM32_GPT_USE_TIM3                  FALSE
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#define STM32_GPT_USE_TIM4                  FALSE
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#define STM32_GPT_USE_TIM5                  FALSE
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#define STM32_GPT_USE_TIM6                  FALSE
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#define STM32_GPT_USE_TIM7                  FALSE
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#define STM32_GPT_USE_TIM8                  FALSE
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#define STM32_GPT_USE_TIM9                  FALSE
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#define STM32_GPT_USE_TIM11                 FALSE
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#define STM32_GPT_USE_TIM12                 FALSE
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#define STM32_GPT_USE_TIM14                 FALSE
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#define STM32_GPT_TIM1_IRQ_PRIORITY         7
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#define STM32_GPT_TIM2_IRQ_PRIORITY         7
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#define STM32_GPT_TIM3_IRQ_PRIORITY         7
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#define STM32_GPT_TIM4_IRQ_PRIORITY         7
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#define STM32_GPT_TIM5_IRQ_PRIORITY         7
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#define STM32_GPT_TIM6_IRQ_PRIORITY         7
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#define STM32_GPT_TIM7_IRQ_PRIORITY         7
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#define STM32_GPT_TIM8_IRQ_PRIORITY         7
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#define STM32_GPT_TIM9_IRQ_PRIORITY         7
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#define STM32_GPT_TIM11_IRQ_PRIORITY        7
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#define STM32_GPT_TIM12_IRQ_PRIORITY        7
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#define STM32_GPT_TIM14_IRQ_PRIORITY        7
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/*
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		||||
 * I2C driver system settings.
 | 
			
		||||
 */
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		||||
#define STM32_I2C_USE_I2C1                  FALSE
 | 
			
		||||
#define STM32_I2C_USE_I2C2                  FALSE
 | 
			
		||||
#define STM32_I2C_USE_I2C3                  FALSE
 | 
			
		||||
#define STM32_I2C_BUSY_TIMEOUT              50
 | 
			
		||||
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
 | 
			
		||||
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
 | 
			
		||||
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
 | 
			
		||||
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
 | 
			
		||||
#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
 | 
			
		||||
#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
 | 
			
		||||
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
 | 
			
		||||
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
 | 
			
		||||
#define STM32_I2C_I2C3_IRQ_PRIORITY         5
 | 
			
		||||
#define STM32_I2C_I2C1_DMA_PRIORITY         3
 | 
			
		||||
#define STM32_I2C_I2C2_DMA_PRIORITY         3
 | 
			
		||||
#define STM32_I2C_I2C3_DMA_PRIORITY         3
 | 
			
		||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * I2S driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_I2S_USE_SPI2                  FALSE
 | 
			
		||||
#define STM32_I2S_USE_SPI3                  FALSE
 | 
			
		||||
#define STM32_I2S_SPI2_IRQ_PRIORITY         10
 | 
			
		||||
#define STM32_I2S_SPI3_IRQ_PRIORITY         10
 | 
			
		||||
#define STM32_I2S_SPI2_DMA_PRIORITY         1
 | 
			
		||||
#define STM32_I2S_SPI3_DMA_PRIORITY         1
 | 
			
		||||
#define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
 | 
			
		||||
#define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
 | 
			
		||||
#define STM32_I2S_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
 | 
			
		||||
#define STM32_I2S_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
 | 
			
		||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * ICU driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_ICU_USE_TIM1                  FALSE
 | 
			
		||||
#define STM32_ICU_USE_TIM2                  FALSE
 | 
			
		||||
#define STM32_ICU_USE_TIM3                  FALSE
 | 
			
		||||
#define STM32_ICU_USE_TIM4                  FALSE
 | 
			
		||||
#define STM32_ICU_USE_TIM5                  FALSE
 | 
			
		||||
#define STM32_ICU_USE_TIM8                  FALSE
 | 
			
		||||
#define STM32_ICU_USE_TIM9                  FALSE
 | 
			
		||||
#define STM32_ICU_TIM1_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_ICU_TIM5_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_ICU_TIM8_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_ICU_TIM9_IRQ_PRIORITY         7
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * MAC driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_MAC_TRANSMIT_BUFFERS          2
 | 
			
		||||
#define STM32_MAC_RECEIVE_BUFFERS           4
 | 
			
		||||
#define STM32_MAC_BUFFERS_SIZE              1522
 | 
			
		||||
#define STM32_MAC_PHY_TIMEOUT               100
 | 
			
		||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
 | 
			
		||||
#define STM32_MAC_ETH1_IRQ_PRIORITY         13
 | 
			
		||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * PWM driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_PWM_USE_ADVANCED              FALSE
 | 
			
		||||
#define STM32_PWM_USE_TIM1                  FALSE
 | 
			
		||||
#define STM32_PWM_USE_TIM2                  FALSE
 | 
			
		||||
#define STM32_PWM_USE_TIM3                  FALSE
 | 
			
		||||
#define STM32_PWM_USE_TIM4                  FALSE
 | 
			
		||||
#define STM32_PWM_USE_TIM5                  FALSE
 | 
			
		||||
#define STM32_PWM_USE_TIM8                  FALSE
 | 
			
		||||
#define STM32_PWM_USE_TIM9                  FALSE
 | 
			
		||||
#define STM32_PWM_TIM1_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_PWM_TIM5_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_PWM_TIM8_IRQ_PRIORITY         7
 | 
			
		||||
#define STM32_PWM_TIM9_IRQ_PRIORITY         7
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * RTC driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_RTC_PRESA_VALUE               32
 | 
			
		||||
#define STM32_RTC_PRESS_VALUE               1024
 | 
			
		||||
#define STM32_RTC_CR_INIT                   0
 | 
			
		||||
#define STM32_RTC_TAMPCR_INIT               0
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * SDC driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_SDC_SDIO_DMA_PRIORITY         3
 | 
			
		||||
#define STM32_SDC_SDIO_IRQ_PRIORITY         9
 | 
			
		||||
#define STM32_SDC_WRITE_TIMEOUT_MS          1000
 | 
			
		||||
#define STM32_SDC_READ_TIMEOUT_MS           1000
 | 
			
		||||
#define STM32_SDC_CLOCK_ACTIVATION_DELAY    10
 | 
			
		||||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    TRUE
 | 
			
		||||
#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * SERIAL driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_SERIAL_USE_USART1             FALSE
 | 
			
		||||
#define STM32_SERIAL_USE_USART2             FALSE
 | 
			
		||||
#define STM32_SERIAL_USE_USART3             FALSE
 | 
			
		||||
#define STM32_SERIAL_USE_UART4              FALSE
 | 
			
		||||
#define STM32_SERIAL_USE_UART5              FALSE
 | 
			
		||||
#define STM32_SERIAL_USE_USART6             FALSE
 | 
			
		||||
#define STM32_SERIAL_USART1_PRIORITY        12
 | 
			
		||||
#define STM32_SERIAL_USART2_PRIORITY        12
 | 
			
		||||
#define STM32_SERIAL_USART3_PRIORITY        12
 | 
			
		||||
#define STM32_SERIAL_UART4_PRIORITY         12
 | 
			
		||||
#define STM32_SERIAL_UART5_PRIORITY         12
 | 
			
		||||
#define STM32_SERIAL_USART6_PRIORITY        12
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * SPI driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_SPI_USE_SPI1                  FALSE
 | 
			
		||||
#define STM32_SPI_USE_SPI2                  FALSE
 | 
			
		||||
#define STM32_SPI_USE_SPI3                  FALSE
 | 
			
		||||
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
 | 
			
		||||
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
 | 
			
		||||
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
 | 
			
		||||
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
 | 
			
		||||
#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
 | 
			
		||||
#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
 | 
			
		||||
#define STM32_SPI_SPI1_DMA_PRIORITY         1
 | 
			
		||||
#define STM32_SPI_SPI2_DMA_PRIORITY         1
 | 
			
		||||
#define STM32_SPI_SPI3_DMA_PRIORITY         1
 | 
			
		||||
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
 | 
			
		||||
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
 | 
			
		||||
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
 | 
			
		||||
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * ST driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_ST_IRQ_PRIORITY               8
 | 
			
		||||
#define STM32_ST_USE_TIMER                  2
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * UART driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_UART_USE_USART1               FALSE
 | 
			
		||||
#define STM32_UART_USE_USART2               FALSE
 | 
			
		||||
#define STM32_UART_USE_USART3               FALSE
 | 
			
		||||
#define STM32_UART_USE_UART4                FALSE
 | 
			
		||||
#define STM32_UART_USE_UART5                FALSE
 | 
			
		||||
#define STM32_UART_USE_USART6               FALSE
 | 
			
		||||
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
 | 
			
		||||
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
 | 
			
		||||
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
 | 
			
		||||
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
 | 
			
		||||
#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
 | 
			
		||||
#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
 | 
			
		||||
#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)
 | 
			
		||||
#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)
 | 
			
		||||
#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
 | 
			
		||||
#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
 | 
			
		||||
#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
 | 
			
		||||
#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
 | 
			
		||||
#define STM32_UART_USART1_IRQ_PRIORITY      12
 | 
			
		||||
#define STM32_UART_USART2_IRQ_PRIORITY      12
 | 
			
		||||
#define STM32_UART_USART3_IRQ_PRIORITY      12
 | 
			
		||||
#define STM32_UART_UART4_IRQ_PRIORITY       12
 | 
			
		||||
#define STM32_UART_UART5_IRQ_PRIORITY       12
 | 
			
		||||
#define STM32_UART_USART6_IRQ_PRIORITY      12
 | 
			
		||||
#define STM32_UART_USART1_DMA_PRIORITY      0
 | 
			
		||||
#define STM32_UART_USART2_DMA_PRIORITY      0
 | 
			
		||||
#define STM32_UART_USART3_DMA_PRIORITY      0
 | 
			
		||||
#define STM32_UART_UART4_DMA_PRIORITY       0
 | 
			
		||||
#define STM32_UART_UART5_DMA_PRIORITY       0
 | 
			
		||||
#define STM32_UART_USART6_DMA_PRIORITY      0
 | 
			
		||||
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * USB driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_USB_USE_OTG1                  TRUE
 | 
			
		||||
#define STM32_USB_USE_OTG2                  FALSE
 | 
			
		||||
#define STM32_USB_OTG1_IRQ_PRIORITY         14
 | 
			
		||||
#define STM32_USB_OTG2_IRQ_PRIORITY         14
 | 
			
		||||
#define STM32_USB_OTG1_RX_FIFO_SIZE         512
 | 
			
		||||
#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
 | 
			
		||||
#define STM32_USB_HOST_WAKEUP_DURATION      2
 | 
			
		||||
 | 
			
		||||
#define STM32_USB_OTG_THREAD_PRIO           NORMALPRIO+1
 | 
			
		||||
#define STM32_USB_OTG_THREAD_STACK_SIZE     128
 | 
			
		||||
 | 
			
		||||
/*
 | 
			
		||||
 * WDG driver system settings.
 | 
			
		||||
 */
 | 
			
		||||
#define STM32_WDG_USE_IWDG                  FALSE
 | 
			
		||||
 | 
			
		||||
#endif /* MCUCONF_H */
 | 
			
		||||
| 
						 | 
				
			
			@ -268,6 +268,38 @@ ifneq ($(findstring STM32F401, $(MCU)),)
 | 
			
		|||
  UF2_FAMILY ?= STM32F4
 | 
			
		||||
endif
 | 
			
		||||
 | 
			
		||||
ifneq ($(findstring STM32F407, $(MCU)),)
 | 
			
		||||
  # Cortex version
 | 
			
		||||
  MCU = cortex-m4
 | 
			
		||||
 | 
			
		||||
  # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
 | 
			
		||||
  ARMV = 7
 | 
			
		||||
 | 
			
		||||
  ## chip/board settings
 | 
			
		||||
  # - the next two should match the directories in
 | 
			
		||||
  #   <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
 | 
			
		||||
  MCU_FAMILY = STM32
 | 
			
		||||
  MCU_SERIES = STM32F4xx
 | 
			
		||||
 | 
			
		||||
  # Linker script to use
 | 
			
		||||
  # - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
 | 
			
		||||
  #   or <keyboard_dir>/ld/
 | 
			
		||||
  MCU_LDSCRIPT ?= STM32F407xE
 | 
			
		||||
 | 
			
		||||
  # Startup code to use
 | 
			
		||||
  #  - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
 | 
			
		||||
  MCU_STARTUP ?= stm32f4xx
 | 
			
		||||
 | 
			
		||||
  # Board: it should exist either in <chibios>/os/hal/boards/,
 | 
			
		||||
  # <keyboard_dir>/boards/, or drivers/boards/
 | 
			
		||||
  BOARD ?= GENERIC_STM32_F407XE
 | 
			
		||||
 | 
			
		||||
  USE_FPU ?= yes
 | 
			
		||||
 | 
			
		||||
  # UF2 settings
 | 
			
		||||
  UF2_FAMILY ?= STM32F4
 | 
			
		||||
endif
 | 
			
		||||
 | 
			
		||||
ifneq ($(findstring STM32F411, $(MCU)),)
 | 
			
		||||
  # Cortex version
 | 
			
		||||
  MCU = cortex-m4
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
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