forked from mirrors/qmk_userspace
LED drivers: register naming cleanups (#22436)
This commit is contained in:
parent
e279c78ba3
commit
dda6e7fb36
51 changed files with 684 additions and 671 deletions
|
@ -20,22 +20,6 @@
|
|||
#include "i2c_master.h"
|
||||
#include "wait.h"
|
||||
|
||||
#define IS31FL3733_COMMANDREGISTER 0xFD
|
||||
#define IS31FL3733_COMMANDREGISTER_WRITELOCK 0xFE
|
||||
#define IS31FL3733_INTERRUPTMASKREGISTER 0xF0
|
||||
#define IS31FL3733_INTERRUPTSTATUSREGISTER 0xF1
|
||||
|
||||
#define IS31FL3733_PAGE_LEDCONTROL 0x00 // PG0
|
||||
#define IS31FL3733_PAGE_PWM 0x01 // PG1
|
||||
#define IS31FL3733_PAGE_AUTOBREATH 0x02 // PG2
|
||||
#define IS31FL3733_PAGE_FUNCTION 0x03 // PG3
|
||||
|
||||
#define IS31FL3733_REG_CONFIGURATION 0x00 // PG3
|
||||
#define IS31FL3733_REG_GLOBALCURRENT 0x01 // PG3
|
||||
#define IS31FL3733_REG_RESET 0x11 // PG3
|
||||
#define IS31FL3733_REG_SW_PULLUP 0x0F // PG3
|
||||
#define IS31FL3733_REG_CS_PULLDOWN 0x10 // PG3
|
||||
|
||||
#define IS31FL3733_PWM_REGISTER_COUNT 192
|
||||
#define IS31FL3733_LED_CONTROL_REGISTER_COUNT 24
|
||||
|
||||
|
@ -59,8 +43,8 @@
|
|||
# define IS31FL3733_CS_PULLDOWN IS31FL3733_PDR_0_OHM
|
||||
#endif
|
||||
|
||||
#ifndef IS31FL3733_GLOBALCURRENT
|
||||
# define IS31FL3733_GLOBALCURRENT 0xFF
|
||||
#ifndef IS31FL3733_GLOBAL_CURRENT
|
||||
# define IS31FL3733_GLOBAL_CURRENT 0xFF
|
||||
#endif
|
||||
|
||||
#ifndef IS31FL3733_SYNC_1
|
||||
|
@ -167,20 +151,20 @@ void is31fl3733_init(uint8_t bus, uint8_t addr, uint8_t sync) {
|
|||
// Sync is passed so set it according to the datasheet.
|
||||
|
||||
// Unlock the command register.
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_COMMANDREGISTER_WRITELOCK, 0xC5);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_COMMAND_WRITE_LOCK, IS31FL3733_COMMAND_WRITE_LOCK_MAGIC);
|
||||
|
||||
// Select PG0
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_COMMANDREGISTER, IS31FL3733_PAGE_LEDCONTROL);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_COMMAND, IS31FL3733_COMMAND_LED_CONTROL);
|
||||
// Turn off all LEDs.
|
||||
for (int i = 0; i < IS31FL3733_LED_CONTROL_REGISTER_COUNT; i++) {
|
||||
is31fl3733_write_register(bus, addr, i, 0x00);
|
||||
}
|
||||
|
||||
// Unlock the command register.
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_COMMANDREGISTER_WRITELOCK, 0xC5);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_COMMAND_WRITE_LOCK, IS31FL3733_COMMAND_WRITE_LOCK_MAGIC);
|
||||
|
||||
// Select PG1
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_COMMANDREGISTER, IS31FL3733_PAGE_PWM);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_COMMAND, IS31FL3733_COMMAND_PWM);
|
||||
// Set PWM on all LEDs to 0
|
||||
// No need to setup Breath registers to PWM as that is the default.
|
||||
for (int i = 0; i < IS31FL3733_PWM_REGISTER_COUNT; i++) {
|
||||
|
@ -188,18 +172,18 @@ void is31fl3733_init(uint8_t bus, uint8_t addr, uint8_t sync) {
|
|||
}
|
||||
|
||||
// Unlock the command register.
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_COMMANDREGISTER_WRITELOCK, 0xC5);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_COMMAND_WRITE_LOCK, IS31FL3733_COMMAND_WRITE_LOCK_MAGIC);
|
||||
|
||||
// Select PG3
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_COMMANDREGISTER, IS31FL3733_PAGE_FUNCTION);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_COMMAND, IS31FL3733_COMMAND_FUNCTION);
|
||||
// Set de-ghost pull-up resistors (SWx)
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_SW_PULLUP, IS31FL3733_SW_PULLUP);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_FUNCTION_REG_SW_PULLUP, IS31FL3733_SW_PULLUP);
|
||||
// Set de-ghost pull-down resistors (CSx)
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_CS_PULLDOWN, IS31FL3733_CS_PULLDOWN);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_FUNCTION_REG_CS_PULLDOWN, IS31FL3733_CS_PULLDOWN);
|
||||
// Set global current to maximum.
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_GLOBALCURRENT, IS31FL3733_GLOBALCURRENT);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_FUNCTION_REG_GLOBAL_CURRENT, IS31FL3733_GLOBAL_CURRENT);
|
||||
// Disable software shutdown.
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_REG_CONFIGURATION, ((sync & 0b11) << 6) | ((IS31FL3733_PWM_FREQUENCY & 0b111) << 3) | 0x01);
|
||||
is31fl3733_write_register(bus, addr, IS31FL3733_FUNCTION_REG_CONFIGURATION, ((sync & 0b11) << 6) | ((IS31FL3733_PWM_FREQUENCY & 0b111) << 3) | 0x01);
|
||||
|
||||
// Wait 10ms to ensure the device has woken up.
|
||||
wait_ms(10);
|
||||
|
@ -259,8 +243,8 @@ void is31fl3733_set_led_control_register(uint8_t index, bool red, bool green, bo
|
|||
void is31fl3733_update_pwm_buffers(uint8_t addr, uint8_t index) {
|
||||
if (g_pwm_buffer_update_required[index]) {
|
||||
// Firstly we need to unlock the command register and select PG1.
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_COMMANDREGISTER_WRITELOCK, 0xC5);
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_COMMANDREGISTER, IS31FL3733_PAGE_PWM);
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_REG_COMMAND_WRITE_LOCK, IS31FL3733_COMMAND_WRITE_LOCK_MAGIC);
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_REG_COMMAND, IS31FL3733_COMMAND_PWM);
|
||||
|
||||
// If any of the transactions fail we risk writing dirty PG0,
|
||||
// refresh page 0 just in case.
|
||||
|
@ -274,8 +258,8 @@ void is31fl3733_update_pwm_buffers(uint8_t addr, uint8_t index) {
|
|||
void is31fl3733_update_led_control_registers(uint8_t addr, uint8_t index) {
|
||||
if (g_led_control_registers_update_required[index]) {
|
||||
// Firstly we need to unlock the command register and select PG0
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_COMMANDREGISTER_WRITELOCK, 0xC5);
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_COMMANDREGISTER, IS31FL3733_PAGE_LEDCONTROL);
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_REG_COMMAND_WRITE_LOCK, IS31FL3733_COMMAND_WRITE_LOCK_MAGIC);
|
||||
is31fl3733_write_register(index, addr, IS31FL3733_REG_COMMAND, IS31FL3733_COMMAND_LED_CONTROL);
|
||||
for (int i = 0; i < IS31FL3733_LED_CONTROL_REGISTER_COUNT; i++) {
|
||||
is31fl3733_write_register(index, addr, i, g_led_control_registers[index][i]);
|
||||
}
|
||||
|
|
|
@ -22,6 +22,25 @@
|
|||
#include <stdbool.h>
|
||||
#include "progmem.h"
|
||||
|
||||
#define IS31FL3733_REG_INTERRUPT_MASK 0xF0
|
||||
#define IS31FL3733_REG_INTERRUPT_STATUS 0xF1
|
||||
|
||||
#define IS31FL3733_REG_COMMAND 0xFD
|
||||
|
||||
#define IS31FL3733_COMMAND_LED_CONTROL 0x00
|
||||
#define IS31FL3733_COMMAND_PWM 0x01
|
||||
#define IS31FL3733_COMMAND_AUTO_BREATH 0x02
|
||||
#define IS31FL3733_COMMAND_FUNCTION 0x03
|
||||
|
||||
#define IS31FL3733_FUNCTION_REG_CONFIGURATION 0x00
|
||||
#define IS31FL3733_FUNCTION_REG_GLOBAL_CURRENT 0x01
|
||||
#define IS31FL3733_FUNCTION_REG_SW_PULLUP 0x0F
|
||||
#define IS31FL3733_FUNCTION_REG_CS_PULLDOWN 0x10
|
||||
#define IS31FL3733_FUNCTION_REG_RESET 0x11
|
||||
|
||||
#define IS31FL3733_REG_COMMAND_WRITE_LOCK 0xFE
|
||||
#define IS31FL3733_COMMAND_WRITE_LOCK_MAGIC 0xC5
|
||||
|
||||
#define IS31FL3733_I2C_ADDRESS_GND_GND 0x50
|
||||
#define IS31FL3733_I2C_ADDRESS_GND_SCL 0x51
|
||||
#define IS31FL3733_I2C_ADDRESS_GND_SDA 0x52
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
#define DRIVER_2_LED_TOTAL 39
|
||||
#define RGB_MATRIX_LED_COUNT (DRIVER_1_LED_TOTAL + DRIVER_2_LED_TOTAL)
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
/* Set led driver current */
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0x9D, 0x9D, 0x44, 0x9D, 0x9D, 0x44, 0x9D, 0x9D, 0x44, 0x9D, 0x9D, 0x44 }
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
/* LED Matrix Configuration */
|
||||
#define LED_MATRIX_LED_COUNT 90
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
/* Set led driver current */
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0x9D, 0x9D, 0x44, 0x9D, 0x9D, 0x44, 0x9D, 0x9D, 0x44, 0x9D, 0x9D, 0x44 }
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
/* RGB Matrix Configuration */
|
||||
#define RGB_MATRIX_LED_COUNT 26
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
|
||||
/* Encoder Configuration*/
|
||||
#define ENCODER_DEFAULT_POS 0x3
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0x98, 0x98, 0x4A, 0x98, 0x98, 0x4A, 0x98, 0x98, 0x4A, 0x98, 0x98, 0x4A }
|
||||
|
||||
|
|
|
@ -44,7 +44,7 @@
|
|||
#define WEAR_LEVELING_LOGICAL_SIZE 2048
|
||||
#define WEAR_LEVELING_BACKING_SIZE (WEAR_LEVELING_LOGICAL_SIZE * 2)
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
/* Set LED driver current */
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0xA6, 0xA6, 0x50, 0xA6, 0xA6, 0x50, 0xA6, 0xA6, 0x50, 0xA6, 0xA6, 0x50 }
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
#define SNLED27351_I2C_ADDRESS_1 SNLED27351_I2C_ADDRESS_VDDIO
|
||||
#define SNLED27351_I2C_ADDRESS_2 SNLED27351_I2C_ADDRESS_GND
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
|
||||
/* Disable DIP switch in matrix data */
|
||||
#define MATRIX_MASKED
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
|
||||
/* DIP switch */
|
||||
#define DIP_SWITCH_MATRIX_GRID { {5, 4} }
|
||||
|
|
|
@ -24,5 +24,4 @@
|
|||
/* RGB Matrix Configuration */
|
||||
#define RGB_MATRIX_LED_COUNT 61
|
||||
|
||||
/* Scan phase of led driver set as SNLED27351_MSKPHASE_9CHANNEL(defined as 0x03 in SNLED27351.h) */
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
|
|
|
@ -37,7 +37,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 30U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0xB8, 0xB8, 0x58, 0xB8, 0xB8, 0x58, 0xB8, 0xB8, 0x58, 0xB8, 0xB8, 0x58 }
|
||||
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0xF8, 0xF8, 0x80, 0xF8, 0xF8, 0x80, 0xF8, 0xF8, 0x80, 0xF8, 0xF8, 0x80 }
|
||||
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0xC4, 0xC4, 0x60, 0xC4, 0xC4, 0x60, 0xC4, 0xC4, 0x60, 0xC4, 0xC4, 0x60 }
|
||||
|
||||
|
|
|
@ -24,7 +24,7 @@
|
|||
#define DRIVER_2_LED_TOTAL 38
|
||||
#define RGB_MATRIX_LED_COUNT (DRIVER_1_LED_TOTAL + DRIVER_2_LED_TOTAL)
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0xA0, 0xA0, 0x48, 0xA0, 0xA0, 0x48, 0xA0, 0xA0, 0x48, 0xA0, 0xA0, 0x48 }
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#define DRIVER_1_LED_TOTAL 84
|
||||
#define LED_MATRIX_LED_COUNT DRIVER_1_LED_TOTAL
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_6CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_6_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE \
|
||||
{ 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 } // 250mA
|
||||
// { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40 } // 127mA
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
|
||||
/* turn off effects when suspended */
|
||||
#define RGB_DISABLE_WHEN_USB_SUSPENDED
|
||||
|
|
|
@ -42,7 +42,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE { 0x98, 0x98, 0x4A, 0x98, 0x98, 0x4A, 0x98, 0x98, 0x4A, 0x98, 0x98, 0x4A }
|
||||
|
||||
/* DIP switch */
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
|
||||
/* Disable DIP switch in matrix data */
|
||||
#define MATRIX_MASKED
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
|
||||
/* DIP switch */
|
||||
#define DIP_SWITCH_MATRIX_GRID { {5, 4} }
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE { 0xFC, 0xFC, 0x70, 0xFC, 0xFC, 0x70, 0xFC, 0xFC, 0x70, 0xFC, 0xFC, 0x70 }
|
||||
|
||||
/* DIP switch */
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#define I2C1_TIMINGR_SCLH 15U
|
||||
#define I2C1_TIMINGR_SCLL 51U
|
||||
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_MSKPHASE_9CHANNEL
|
||||
#define SNLED27351_PHASE_CHANNEL SNLED27351_SCAN_PHASE_9_CHANNEL
|
||||
#define SNLED27351_CURRENT_TUNE { 0xC4, 0xC4, 0x60, 0xC4, 0xC4, 0x60, 0xC4, 0xC4, 0x60, 0xC4, 0xC4, 0x60 }
|
||||
|
||||
/* DIP switch */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue